As the speed and file capacity of workstations and personal computers increases, the demand for high resolution intelligent display adapters also increases. Large graphic applications formerly limited to mainframe computers having dedicated graphic display terminals can use this increased capability to migrate their graphic applications to stand alone systems. The present invention describes functions that can be incorporated into a video display adapter to provide, in stand alone work stations, the graphic functions and performance required by such complex graphic applications.
Such increased capability display adapters are especially needed for such small stand alone systems as the IBM PC/AT and the IBM RT-PC which can provide high-performance, moderate-cost adapter functions which cover a very broad spectrum of applications.
The memory organization of the frame buffer is a limiting factor to the update performance of frame buffered raster scan displays. The memory organization determines how many and which pixels can be accessed in a single memory cycle, and hence limits the number of pixels that can be updated in parallel by the update hardware. High performance displays frequently allow parallel update to the frame buffer effectively resulting in a lower memory cycle time per pixel.
The parallel update required is dependent upon the size and shape of the objects being drawn into the frame buffer. Hence, if the only objects being drawn were long horizontal lines, an organization which allowed the parallel access of sixteen or thirty-two horizontal pixels would be ideal. Similarly, if the only objects displayed were six by eight characters, then a memory organization that allowed the parallel access of a six by eight array of pixels would be perfect.
An added benefit to frame buffer memory organizations is the ability to access these arrays of pixels at any arbitrary pixel boundary. If the above example of the parallel access of sixteen horizontal pixels limits the location of the left edge to be on a sixteen pixel boundary, then the horizontal line drawer would find its maximum efficiency only if the line started on sixteen pixel boundaries, an unlikely case. Access to sixteen pixels whose left edge can be at any desired pixel boundary is more efficient. In the present description, this type of parallel access will be called "pixel aligned" access.
The implementation of memory organizations determines the cost and complexity of frame buffered systems and their associated update hardware. The memory organization and its implementation hence becomes critical in determining the cost and functionality of frame buffered displays. Because of the nature of memory chips, the complexity of the frame buffer organization is uniquely determined by the number of memory chips and the number of unique signal wires connected to them. These memory wires consist of the address wires (usually multiplexed into row address and column address signals), data wires and control signals (row address strobes, column address strobes, and the write enables).
U.S. Pat. No. 4,435,792 of A. Bechtolsheim issued Mar. 6, 1984 and entitled "RASTER MEMORY MANIPULATION APPARATUS" provides a frame buffer organization which allows the access of sixteen pixel aligned horizontal pixels. This is achieved by using sixteen memory chips (64 kilobits each) to realize a 1K by 1K frame buffer. The ability to access a pixel aligned word is achieved by strobing column addresses to different chips depending upon the left boundary of the desired word. The implementation uses one address bus, but sixteen column address strobe wires. The first address is driven and the appropriate chips strobed, followed by the second address and the strobe of the rest of the chips. This implementation requires a longer memory cycle but only eight address signals.
An article by Robert F. Sproull, Ivan E. Sutherland, Alistair Thompson, Satish Gupta, and Charles Minter, entitled "THE EIGHT BY EIGHT DISPLAY", ACM Transactions on Graphics, Vol. 2, No. 1, Jan. 1983, pp. 32-56 describes the implementation of the access to an eight by eight array of pixels that could be pixel aligned to optimize the access for different operations. The eight by eight display had eight sets of addresses (eight wires each) which could deliver different addresses to different columns of the eight by eight array of memory chips. The memory organization used provided separate row addresses by using the same address wires and providing different column strobes, and provided separate column addresses by driving different addresses on different columns.
The Eight by Eight Display could read or write all 64 pixels. Hence, an eight bits per pixel frame buffer would use five hundred and twelve (64.times.8) bits of data. Obviously, such a large number of bits can be processed only by an array of processors, or require additional multiplexers, which would reduce the number of bits read from the frame buffer to the size of the data bus. In a single process system such a large number of I/O and address lines is too large to be acceptable. The present invention describes a frame buffer memory organization, which has a reduced number of address, data, and control wires, but still allows full pixel aligned addressability to the frame buffer.